1. Field of the Invention
The present invention relates to a semiconductor memory device and more particularly, to a semiconductor memory device such as a Dynamic Random Access Memory (DRAM) provided with stacked capacitor-type memory cells and its fabrication method.
2. Description of the Related Art
Stacked capacitor-type DRAMs effective in increasing capacitance of a storage capacitor per unit cell area have so far been proposed, in which each memory cell is provided with an MOS transistor as a transfer gate and a stacked capacitor for charge storage. An example of such DRAMs is an FIN-structured stacked capacitor-type DRAM cell disclosed in the Japanese Examined Patent Publication No. 3-20905.
FIG. 1A through FIG. 1C are cross sections vertical to word lines of the FIN-structured stacked capacitor-type cell and FIG. 2A through FIG. 2C are cross sections vertical to bit lines of the same, each of which shows a fabrication sequence of the cell.
In FIGS. 1C and 2C, a field oxide film 22 for device isolation is formed on the surface of a P-type silicone substrate 21. In each of active areas surrounded by the field oxide film 22 an MOS transistor is formed. Each of the MOS transistors is composed of an N-type diffusion layer 25s forming a source region, an N-type diffusion layer 25d forming a drain region and a gate electrode 24g formed on a gate oxide film 23.
As seen from FIGS. 1C and 2C, the N-type diffusion layers 25 forming the source region are provided for the respective transistors and each of the N-type diffusion layers 25d forming the drain regions is provided for the two transistors adjacent to each other. The gate electrodes 24g are respectively connected to corresponding word lines 24w formed on the field oxide film 22. The gate electrodes 24g and the word lines 24w are both made of polysilicon.
The surfaces of the active areas, the gate electrodes 24g and the word lines 24w and the uncovered surface of the field oxide film 22 are covered with a first inter-layer insulation film. On the surface of the first inter-layer insulation film 26 bit lines 35 made of tungsten silicide are formed. A second inter-layer insulation film 27 is formed on the surfaces of the bit lines 35 and the uncovered surface of the first inter-layer insulation film 26.
A silicone nitride film 39 is formed on the second inter-layer insulation film 27 and on the film 39 an opposed electrode 28 of the storage capacitor is formed. Charge storage electrodes 31 of the capacitors, each of which has a cross section like a "T" character, are formed to be buried in the opposed electrode 28. The entire surfaces of the charge storage electrodes 31 buried in the opposed electrode 28 are covered with insulation films 29, respectively.
Bottom ends of the charge storage electrodes 31 are in contact with the surfaces of the corresponding N-type diffusion layers 26s as the source regions through corresponding contact holes 38. The holes 38 are formed through the silicone nitride film 39, the second inter-layer insulation film 27 and the first inter-layer insulation film 26, respectively. Thus, the T-shaped charge storage electrodes 31 are electrically connected to the N-type diffusion layer 26s as the source regions, respectively.
Each of the opposed electrodes 28, the insulation films 29 and the charge storage electrodes 31 constitutes each of the storage capacitors. These capacitors are provided on the second inter-layer insulation film 27, in other words, they are stacked over the MOS transistors.
The DRAM memory cells having the above structure are fabricated through the following sequence:
First, as shown in FIGS. 1A and 2A, the field oxide film 22 of about 500 nm in thickness is selectively formed on the surface of the P-type semiconductor substrate 21 using a conventional selective oxidation technique so that the active regions are formed on the surface of the substrate 21. The active regions of the substrate 21 are then ion-implanted for controlling the threshold voltage of the MOS transistors.
The gate oxide films of about 15 nm in thickness are grown on the respective active regions and then, a polysilicon film of about 250 nm in thickness is grown all over the substrate 21. Phosphorus (P) is diffused into the polysilicon film to reduce its sheet electric resistance to a desired level and then, the polysilicon film is etched to a desired pattern using a photolithography technique. Thus, the gate electrodes 24g and the word lines 24w are obtained.
Next, with the field oxide film 22 and the gate electrodes 24g as a mask, phosphorus (P) ions are implanted into the substrate 21 with a dose of about 10.sup.13 cm.sup.-2 and the substrate 21 is heat-treated. This results in the N-type diffusion layers 25s and 25d to function as the source and drain regions.
A silicon oxide film and a BPSG film containing as impurities boron (B) and phosphorus (P) are successively formed over the surface of the substrate 21 using a Chemical Vapor Deposition (CVD) technique to form the first inter-layer insulation film 26 of about 350 nm in thickness.
Using a photolithography technique, a wiring layer (not shown) is formed on the first inter-layer insulation film 26 to make contacts for the bit lines 35, and contact holes (not shown) for connecting the diffusion layers 26s and 25d and the gate electrodes 24g are formed in the insulation film 26. A tungsten silicide film of about 150 nm in thickness is formed on the first inter-layer insulation film 26 by a sputtering technique and patterned the tungsten silicide film by a photolithography technique. Thus, the bit lines 35 made of tungsten silicide are obtained.
A BPSG film of about 400 nm in thickness is formed on the entirety of the first inter-layer insulation film 26 and is reflowed to be flattened, resulting in the second inter-layer insulation film 27. A silicone nitride film 39 of about 20 nm in thickness is grown on the entirety of the second inter-layer insulation film 27 and then, a silicon oxide film 36 of about 100 nm in thickness is grown on the entirety of the silicon nitride film 39.
Using a photolithography technique, the silicone oxide film 36, the silicone nitride film 39, the second inter-layer insulation film 27 and the first inter-layer insulation film 26 are selectively etched to form the contact holes 38 which extend to the surfaces of the corresponding N-type diffusion layers 35s. The cross sections of the device at this time are shown in FIGS. 1A and 2A.
Subsequently, the polysilicon film of about 300 nm in thickness is grown on the entirety of the silicon oxide film 36. Phosphorus is diffused into the polysilicon film 36 to reduce its sheet electric resistance to a desired level and then the polysilicon film 36 is patterned to obtain the charge storage electrodes 31. The silicon oxide film 36 is then removed by etching using buffered hydrogen fluoride. The charge storage electrodes 31 have each T-shaped cross sections. The state at this time is shown in FIGS. 1B and 2B.
Next, as shown in FIGS. 1C and 2C, a silicon nitride film of about 70 nm in thickness is grown and the surface thereof is oxidized in a steaming atmosphere to form the insulation films 29 of the storage capacitors. The insulation films 29 respectively cover the entire surfaces of the charge storage electrodes 31, which are projecting from the silicon nitride film 39.
A polysilicon film of about 150 nm in thickness is grown on the silicon nitride film 39 and its sheet electric resistance is reduced to a desired level by phosphorus diffusion. The polysilicon film is then patterned to form the opposed electrode 28 of the capacitors. The charge storage electrodes 31 are buried in the opposed electrode 28.
Subsequently, although illustration is omitted, a third inter-layer insulation film is formed on the entire surface of the opposed electrode 28. Contact holes are formed in the third inter-layer insulation film and then, a metallic wiring layer is formed thereon. As a result, the opposed electrode 28 is electrically connected to the metallic wiring layer through the contact holes.
Thus, the stacked capacitor-type DRAM cells with the FIN-structure are obtained.
In the conventional stacked capacitor-type DRAM cells, not only the top or upper faces of the charge storage electrodes 31 but also the bottom or lower faces thereof can serve as capacitors. Therefore, the area of the charge storage electrodes 31 can be expanded by using an upper area over the bit lines 35 and as a result, the capacitance value per unit cell area of the conventional stacked capacitor-type DRAM cells with the FIN-structure can be enlarged about 1.5 times as much as those of conventional stacked capacitor-type DRAM cells without the FIN-structure.
The conventional FIN-structured stacked capacitor-type DRAM cells, however, have a problem that the upper wing-like parts of the charge storage electrodes 31 are easily broken due to mechanical shocks occurring in centrifugal drying, vacuum drawing or the like during the fabrication process shown in FIGS. 1B and 2B since the charge storage electrodes 31 are supported by only their pillar parts buried in the corresponding contact holes 38.
In addition, the conventional DRAM cells have another problem that when the charge storage electrodes 31 are sheered off in centering to the corresponding contact holes 38 during the process shown in FIGS. 1B and 2B, the top parts of the electrodes 31 are formed into undesired shapes as well as the second inter-layer insulation film 27 is partially etched as shown in FIG. 3. In FIG. 3, charge storage electrodes 31a whose top parts are not of T-shape cross sections are illustrated.
Further, they have still another problem that the silicon nitride film 39 and the silicon oxide film 36 are staked with each other during the fabrication process shown in FIGS. 1A and 2A, so that the silicon nitride film 39 may project during the process of forming the contact holes 38 or that of pre-treatment for the metallic wiring layer formed on the third inter-layer insulation film by sputtering, which adversely affecting coverage of the metallic wiring layer.